This invention relates to the field of computers and computer systems. More particularly, the present invention relates to a method and apparatus for incorporating bus ratio strap options in chipset logic.
In recent years, the price of personal computers (PCs) have rapidly declined. As a result, more and more consumers have been able to take advantage of newer and faster machines. One of the fast growing sectors of the computer industry involves mobile computing. Users in both the business and home markets are now purchasing notebook computers for use on the road. Unlike desktop computers that are powered by an alternating current (AC) source, notebook computers usually run off a battery supply. If a mobile computer is operating at the same performance level as a desktop machine, the power is drained relatively quickly.
In order to extend battery life of mobile computers without widening the performance gap with desktop counterparts, computer manufacturers and designers have instituted power saving technology. One attempt to reduce power consumption entails the use of low power circuit devices. Another power saving method is to use software in controlling system power and shutting down system devices that are not needed.
Another power saving technique is the use of dual-mode mobile processor technology, which relies on the fact that there is a linear relationship between the clock frequency at which a microprocessor operates and the power dissipation of the microprocessor. Dual-mode mobile processor technology allows a mobile PC user to operate the processor at a high performance, high frequency mode when the system is plugged into a wall outlet and automatically switch the processor to a lower performance, lower frequency mode when the system is running solely on a battery. In order to manipulate processor clock frequency in computer systems, methods and circuits are being developed to provide greater control over clock signals.
Some processor designs have included a feature for changing the operating clock frequency. The bus ratio is the multiplier factor used to multiply the frequency of the external clock signal for use within the processor. In one example, the processor clock frequency ratio may be adjusted by setting the state of four pins on the front side of the processor bus. When the processor resets, the new bus ratio is latched into the processor clock circuitry.
Present designs also use external pull-up or pull-down resistors in conjunction with a multiplexer circuit to apply bus ratio setting during a reset sequence. A number of pull-up and pull-down components and circuitry have to be designed into the board assembly in order to enable all desired bus ratio settings. If a bus ratio is controlled through four signals, at least nine components (four pull-ups, four pull-downs, and a multiplexer) have to be included in the board design in order to provide two bus ratio settings. Furthermore, the only way the bus ratio setting can be changed after the system is built is to open up the computer and physically alter the motherboard. Hence, another design problem entails determining what bus ratio settings to maintain on the motherboard.
FIG. 1 is block diagram of a prior art circuit 100 for changing bus ratios. In this example circuit, four control signals 165 are used to control the bus ratio setting for processor 160. The control signals 165 are outputs of a multiplexer 155. Multiplexer 155 switches different input signals to its output pins based on the setting on a select signal 140. Two settings 110, 120 of bus ratios and control lines from the chipset are input signals to the multiplexer 155 here. The bus ratio settings 110, 120 are determined by connecting jumpers between input pins to the multiplexer 155 and pull-up resistors 130 and pull-down 135 jumpers. The bus ratio settings are made when system is assembled. In order for a user to modify the bus ratio settings, a user would have to open up the computer and physically adjust the pull-down 135 connections.
A method for incorporating bus ratio strap options in chipset logic is described. The method of one embodiment first fabricates a register and multiplexer in chipset logic. The register is programmed with a bus ratio setting. A bus ratio setting is selected to be the output from the multiplexer. The selected bus ratio setting is driven out from the multiplexer to output pins.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.